Essentially, a computer consists at least of:


The central processing unit (CPU) performs the operations of a computer.

The operations executed by a processor are called instructions.

The rate of a processor is determined by the frequency of its clock.

Instructions are executed in a certain number of clock cycles.

Modern CPUs are pipelined and can execute multiple instructions in several stages.

On modern architectures, Most of the instructions are pipelined, which means that a new instruction can be issued every cycle.


Throughput is how frequently a particular instruction can be issued.


Latency is the minimum delay between dependent instructions.


The more complex instructions are implemented as a combination of simpler instructions known as micro-instructions (or microcode).

Micro-instructions can increase parallelism at the instruction level, which is especially good for out-of-order execution.

In non–performance-critical code, microcoded instructions reduce the instruction cache usage.

However, in performance-critical code, microcoded instructions can affect performance.


A CPU is made of several components.

Modern CPUs are divided in individual cores.

Each core has its own set of components, but some memory can be shared.


The arithmetic logic unit (ALU) performs unary and binary integer arithmetic operations, logical operations, and bit shifting operations.


The floating point unit (FPU) performs floating point arithmetic operations.


The vector processing unit (VPU) performs floating point and integer operations on multiple data in parallel.

Vector processing is known as Single Instruction, Multiple Data (SIMD).

In modern CPUs, the FPU operations are handled by the VPU.


The memory management unit (MMU) performs the translation of virtual memory addresses to physical addresses.


The control unit (CU) directs the operation of the processor by controlling the flow of data between the units of the CPU.

The control unit handles branch prediction and out of order execution of instructions.


Registers are accessed directly by the the processor units.

They are the most frequently-used memory in a computer and have the fastest access speed.

A processor contains several kinds of registers including:

General-purpose registers

The general-purpose registers include the data registers, and the address registers

Special-purpose registers

The special-purpose registers include the instruction pointer register, the stack pointer register, the base pointer register, and the status register.

Cache Memory


The system memory is known as random-access memory (RAM).

In modern computers, there are two kind of RAM: SRAM and DRAM.


Static RAM (SRAM) is faster than dynamic RAM but more expensive to produce.

A SRAM cell is composed of several transistors that requires constant power.

The state of the cell is stable and SRAM can be read almost immediately.


Dynamic RAM (DRAM) is simpler than static RAM.

A DRAM cell is composed a single transistor and capacitor.

The capacitor needs to be constantly refreshed and it takes some time for the capacitor to be charged and discharged.

The state of the cell is accessed with a delay that limits the speed of DRAM.

Modern computers use synchronous DRAM (SDRAM).

There are two kind of SDRAM: SDR and DDR.

The difference between single data rate (SDR) and double data rate (DDR) is the amount of data that is transported per cycle.

North Bridge and South Bridge

Computers were designed with a north bridge and south bridge chipset architecture.

In modern computers, the functions of the north bridge are usually included in the processor itself; and the south bridge is replaced by the Platform Controller Hub (PCH) companion chip.

DMA Controller

The direct memory access (DMA) controller performs bulk data transfers, reading data from a source address range and writing the data to a different address range.

The DMA controller transfers data as efficiently as possible, reading and writing data at the maximum pace allowed by the source or destination.

The DMA controller transfers data without intervention from the CPU.

  1. The CPU prepares the DMA controller for a transaction.
  1. The CPU enables the DMA controller.
  1. When the DMA transaction ends, the DMA controller can generate an interrupt request (IRQ).
  1. The CPU can determine if a transaction is in progress, or has ended through a status register.